Sometimes we need to debug a module containing a microprocessor implemented in FPGA. Often the program is enclosed in ELF file – leaving us with no access to the program source code. In these cases we can learn how the program functions by analyzing the machine code for the microprocessor. But first, the assembly code needs to be extracted from the ELF file. Let me show you how to get disassembled code from ELF file in Vivado/Vitis.
I’m happy to announce that my first paper submitted to Electronics Journal has recently been published. The article entitled: “Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA” describes the concept and verification of jitter level comparison methodology. Also the measurements of multiple different Artix 7 FPGA configurations are also presented.
The ability to easily access or modify the contents of a memory instantiated in FPGA chip via a computer can be very helpful during verification or debugging. In case of AMD/Xilinx chips and Vivado IDE, this can be achieved using a combination of several IPs and Tcl commands.
Adding multiple similar constraints in FPGA design can be tedious. A very common one is false path definition for each synchronization chain. Fortunately, in Vivado the XDC constraints are essentially Tcl commands. Therefore, we can easily create the false path constraints automation.
How to resolve Invalid clock redefinition on a clock tree timing critical warning in Xilinx Vivado. What is the reason for this to occur and how to prevent the warning from occurring.
Any FPGA design requires constraints file. At least external (package) pin definition and I/O standard for each of the top-level port. Each constrain can be defined in a separate line, but in Vivado a single line can also specify multiple constraints.
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