VHDL configuration

I have recently had a chance to briefly play with a feature of VHDL I have never used before – configuration. Here I’ve gathered my thoughts and findings in this topic. Partially as sort of ‘note to myself’ and hopefully in the future I will have time to get some more experience with this part of the VHDL language.

How to use shared variables in VHDL

Since VHDL93, shared variables are available for developers to use in their designs. Since then the language evolved and introduced new options and. Currently it’s not immediately obvious how to correctly use a shared variable. This may lead to warnings during simulation, which can be fixed quite easily.

Constant value override from VHDL testbench

The VHDL language provides various ways to create testbenches for design verification. Since version VHDL-2008, it supports force and release statements for signal value injection. But sometimes we might want to override the constant value in testbench i.e. during configurable (via constants) module verification. How can we solve this problem?

Automatic differentiation between simulation and synthesis

Depending on the design, a simulation can take a significant amount of time. In some cases the verification time can be reduced by changing several specific values, such as delays for communication with external devices or address ranges. Often these values are defined using constants values, which can be changes manually whether a simulation or synthesis is performed. But it can be also done automatically in both VHDL and Verilog.

The optimal way of creating memory model in VHDL

During the development of a block communicating with an external chip, a behavioral model of this device can be very helpful. Sometimes such model can be found online, but often we need to create it ourselves. One type of external chip frequently connected to the FPGA is some kind of volatile or non-volatile memory. Unfortunately, in VHDL it is often implemented not optimally.