Automatic differentiation between simulation and synthesis

Andrzej Wojciechowski

Depending on the design, a simulation can take a significant amount of time. In some cases the verification time can be reduced by changing several specific values, such as delays for communication with external devices or address ranges. Often these values are defined using constants values, which can be changes manually whether a simulation or synthesis is performed. But it can be also done automatically in both VHDL and Verilog.

The encountered problem

Suppose you are developing a module that is intended to perform tasks that can take up a relatively long time in a simulation, but are expected to be quick in hardware tests. Examples of such functionalities include:

  • relatively slow communication with external components – can be achieved using system clock counter to avoid the generation of a separate clock domain
  • internal or (more often) external memory communication – the memory’s address space can easily be big enough to unnecessarily extend the simulation time
  • probably many more that I haven’t though about at the moment

In all cases the verification in simulation of the designed functionality is required. But it might not be required (and it often is not required due to this practical reasons) to simulate with the target speed or the whole memory address space (or other similar cases). Most often, proper constant value(s) define the value responsible for mentioned issues – whether declared or coded as magic numbers.

A naive approach

One way to improve a simulation time is by manually changing the aforementioned constant values. It might not be a problem if there is one such value. But in case there are multiple of them, each would need to be updated each time the developer switches from simulation to synthesis (or the opposite way).

In order to solve this issue, we can implement a function that simply selects one of two values based on a parameter. Then each constant value that needs to have a different value for simulation and for synthesis, can be defined using this function. Now all values can be updated using a single specific constant.

However, that still leaves the responsibility for updating a parameter on a developer. I personally prefer to make a computer do such work whenever I can. Like change a value automatically, rather than relay on my own memory. After all, computers are much better at not forgetting to do something than humans.

An automatic approach

Now the question is: can we automatically detect if a module is being simulated or synthesized, without any additional 1 user action? It turns out we can!

In order to achieve this, we need to use another VHDL/Verilog functionality called pragmas or compiler directives. Below are links to 2 great articles about this constructs from Sigasi blog:

Very similar constructs are also present in Verilog/SystemVerilog.

Now we simply need to utilize the correct pragma. According to Sigasi’s posts, the safest choice is pragma translate_off/on. An example of automatic detection simulation and synthesis detection with corresponding function is given below.

package demo_pkg is

constant C_IS_SIMULATION : boolean := FALSE
-- pragma translate_off
-- pragma translate_on

function sim_synth_val(
   simul_val   : integer;
   synth_val   : integer
) return integer;


package body demo_pkg is

function sim_synth_val(
   simul_val   : integer;
   synth_val   : integer
) return integer is
   if C_IS_SIMULATION then
      return simul_val;
      return synth_val;
   end if;
end function sim_synth_val;

end package body;

  1. anything more than actually running the simulation or synthesis

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