How to get disassembled ELF file in Vivado/Vitis

Sometimes we need to debug a module containing a microprocessor implemented in FPGA. Often the program is enclosed in ELF file – leaving us with no access to the program source code. In these cases we can learn how the program functions by analyzing the machine code for the microprocessor. But first, the assembly code needs to be extracted from the ELF file. Let me show you how to get disassembled code from ELF file in Vivado/Vitis.

My article in Electronics Journal

I’m happy to announce that my first paper submitted to Electronics Journal has recently been published. The article entitled: “Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA” describes the concept and verification of jitter level comparison methodology. Also the measurements of multiple different Artix 7 FPGA configurations are also presented.

FPGA memory accessible from Vivado

The ability to easily access or modify the contents of a memory instantiated in FPGA chip via a computer can be very helpful during verification or debugging. In case of AMD/Xilinx chips and Vivado IDE, this can be achieved using a combination of several IPs and Tcl commands.