Setting Vivado design constraints

Any FPGA design requires constraints file. At least external (package) pin definition and I/O standard for each of the top-level port. Each constrain can be defined in a separate line, but in Vivado a single line can also specify multiple constraints.

The default Vivado constraints

There is a known but sometimes forgotten way to set all object’s properties using a single XDC/Tcl command. I tend to forget this method, so for future reference I decided to add this post. By default you can define each parameter separately. For example, in order to define the external pin location and I/O standard you’d need the following lines in the XDC file:

set_property PACKAGE_PIN H10 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports clk]

Multiple constraints in a single line

We can shorten the above code using Tcl dictionaries. The previous constraints can be also written as:

set_property -dict {PACKAGE_PIN H10 IOSTANDARD LVCMOS18} [get_ports clk]

List of resources:

• Xilinx UG835 – Vivado Design Suite Tcl Command Reference Guide
• Xilinx support – 62465