I’m happy to announce that my first paper submitted to Electronics Journal has recently been published. The article entitled: “Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA” describes the concept and verification of jitter level comparison methodology. Also the measurements of multiple different Artix 7 FPGA configurations are also presented.
The article details
I’ve been working on this paper for the past few months as it was one of the requirements during my PhD studies. So as you can guess, it’s a big relief for me to know that it’s accepted.
The article contains several potentially interesting information. The jitter or phase comparator system using dual TDL approach. Two separate architectures are compared:
- utilizing only flip flops
- utilizing latches and flip flops
The configuration with latches turned up to perform better than the other. Also the temperature influence was tested. Finally, many different FPGA clocking configurations were compared – with some interesting results.
The idea for the experiments and the paper emerged from my “main” PhD project. The jitter comparison methodology was a sort of a side effect. It happened to be quicker to finish and measure compared to the “primary” project. The “main” project involves phase and frequency manipulation of several clock signals, using FPGA clocking resources (with potential usage of non-clock capable input pins) and phase comparison using a modified version of the jitter measurement system presented in the article.
I hope you will find important information for yourself in this paper. You can find the article here.
