Constant value override from VHDL testbench

Andrzej Wojciechowski

The VHDL language provides various ways to create testbenches for design verification. Since version VHDL-2008, it supports force and release statements for signal value injection. But sometimes we might want to override the constant value in testbench i.e. during configurable (via constants) module verification. How can we solve this problem?

The encountered problem

Recently I came across a need to change the value of a VHDL constant in a testbench I was creating for a configurable module verification. Some of the module’s functionalities could be modified using various constants. And of course I needed to verify that the module works correctly in multiple configuration options. Therefore, in order to avoid constantly changing the constants in a design’s package file for verification, I needed a way to modify the constants’ values from a testbench.

Force statement

The force and release statements introduced in VHDL-2008 are great tools for design verification. Unfortunately these statements only work for signals, and not for other VHDL objects. That’s very unfortunate in this case. But there is a way to use this method – I’ll cover that later.

Generics override

The first solution that comes to mind is the use of generics. A generic value can be overridden when running a testbench by using a flag (often -G or -P flag). But that limits us to a single value per simulation run. That’s not the best level of flexibility, but certainly can be very useful in many cases.

Is also enables initial memory state injection.

Using the force statement for constants override

Like previously mentioned, there is a way to use force and release statements on constant objects. We simply need to assign the constant value to a newly created signal asynchronously and then use this signal everywhere we would use the constant previously. This enables us to effectively override the constant value from a testbench by using force and release statements on the created signal. And there is no impact on the synthesis as well.

Here is a simple example of how this method:

Tested module:

entity demo is
port (
end demo;

architecture arch of demo is

constant C_CONFIGURATION   : integer := 3; -- the constant value we want to override from testbench
signal config              : integer;      -- the dummy signal for constant assignment


config                     <= C_CONFIGURATION;

end arch;


entity demo_tb is
end demo_tb;

architecture test of demo_tb is

   alias a_config is <<signal path_to_configuration_signal : integer >>;

   force a_config <= 1;
end process;

end test;

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