Blog

Invoice date parser

I try to keep the documents in some order. In case of the invoices, I prefer to store each of them in a folder named with corresponding month. That’s not the same as the month when I’ve downloaded or received the invoice. I needed to extract a date from each invoice, so I’ve decided to create an invoice date parser script. This task turned out to be more difficult than I initially expected.

Handy AppleScript libraries

I have recently came across several amazingly useful libraries for MacOS tasks automation with AppleScript. Even though they exists for several years now, for a long time I had no idea these existed. So I’ve decided to share my discovery here and hope it will help somebody in the future.

GitLab CI template: YAML anchor vs. ‘extends’ keyword

Creating a CI pipeline can get tedious quite quickly. Fortunately, there are a couple of ways to avoid creating multiple similar jobs. In case of GitLab’s .gitlab-ci.yml files, we can use job templates. Based on templates, we can easily define the actual jobs. The two most common methods to use a GitLab CI template are YAML anchors and ‘extends’ keyword. These are very similar, but there is at least one not obvious difference.

LaTeX documents accessible in the repository with CI

LaTeX is a very popular and in my opinion an optimal tool for creating documents larger than a couple of pages. It is often used for technical documentation and kept in a version control system, such as git. Usually, only LaTeX source files are stored in a repository, unlike the final PDF files. But is there a way to make a generated PDF document always up to date and accessible in the repository, without versioning the actual file? It turns out that it’s possible with continuous integration (CI).

How to use shared variables in VHDL

Since VHDL93, shared variables are available for developers to use in their designs. Since then the language evolved and introduced new options and. Currently it’s not immediately obvious how to correctly use a shared variable. This may lead to warnings during simulation, which can be fixed quite easily.

Constant value override from VHDL testbench

The VHDL language provides various ways to create testbenches for design verification. Since version VHDL-2008, it supports force and release statements for signal value injection. But sometimes we might want to override the constant value in testbench i.e. during configurable (via constants) module verification. How can we solve this problem?

The best way to use monitor(s) with multiple computers

For quite some time now my desk setup consists of two monitors and several computers connected to them. The number varies between 2 up to 4, which is a maximum number of inputs my monitors support. Sometimes I use one of the monitors with one computer, and the second with a different computer. Other times I use both monitors with the same computer and switch both of them to use with another PC. I’ve tried multiple different ways to conveniently control which computer’s screen is displayed and I think I’ve found the best solution.

Automatic differentiation between simulation and synthesis

Depending on the design, a simulation can take a significant amount of time. In some cases the verification time can be reduced by changing several specific values, such as delays for communication with external devices or address ranges. Often these values are defined using constants values, which can be changes manually whether a simulation or synthesis is performed. But it can be also done automatically in both VHDL and Verilog.

The optimal way of creating memory model in VHDL

During the development of a block communicating with an external chip, a behavioral model of this device can be very helpful. Sometimes such model can be found online, but often we need to create it ourselves. One type of external chip frequently connected to the FPGA is some kind of volatile or non-volatile memory. Unfortunately, in VHDL it is often implemented not optimally.